Agenda

Advances in Analog Circuit Design

27th Workshop on Advances in Analog Circuit Design

The AACD workshops are a high-quality series of events held all over the world. They have been held annually since 1992 with the aim of bringing together a large group of people working at the forefront of analog circuit design. The workshops offer the opportunity to discuss new possibilities and future developments whilst networking with key figures from across the analog design community.

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PhD Thesis Defence

Front-End ASICs for 3-D Ultrasound: From Beamforming to Digitization

Chao Chen

Program:
12:00 - 12:15 Introductory presentation
12:30 - 13:30 Public defense
13:45 - 14:00 Diploma ceremony
Address: Senaatszaal of the Aula Congress Center

SUMMARY
This thesis describes the analysis, design and evaluation of front-end application-specific integrated circuits (ASICs) for 3-D medical ultrasound imaging, with the focus on the receive electronics. They are specifically designed for next-generation miniature 3-D ultrasound devices, such as transesophageal echocardiography (TEE), intracardiac echocardiography (ICE) and intravascular ultrasound (IVUS) probes. These probes, equipped with 2-D array transducers and thus the capability of volumetric visualization, are crucial for both accurate diagnosis and therapy guidance of cardiovascular diseases. However, their stringent size constraints, as well as the limited power budget, increase the difficulty in integrating in-probe electronics. The mismatch between the increasing number of transducer elements and the limited cable count that can be accommodated, also makes it challenging to acquire data from these probes. Front-end ASICs that are optimized in both system architecture and circuit-level implementation are proposed in this thesis to tackle these problems.
The techniques described in this thesis have been applied in several prototype realizations, including one LNA test chip, one PVDF readout IC, two analog beamforming ASICs and one ASIC with on-chip digitization and datalinks. All prototypes have been evaluated both electrically and acoustically. The LNA test chip achieved a noise-efficiency factor (NEF) that is 2.5 × better than the state-of-the-art. One of the analog beamforming ASIC achieved a 0.27 mW/element power efficiency with a compact layout matched to a 150 µm element pitch. This is the highest power-efficiency and smallest pitch to date, in comparison with state-of-the-art ultrasound front-end ASICs. The ASIC with integrated beamforming ADC consumed only 0.91 mW/element within the same element area. A comparison with previous digitization solutions for 3-D ultrasound shows that this work achieved a 10 × improvement in power-efficiency, as well as a 3.3 × improvement in integration density.

The dissertation can be found in the TU Delft repository: http://doi.org/10.4233/uuid:a5002bb0-4701-4e33-aef6-3c78d0c9fd70

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